DC/DC power management systems generally regulate static or switched-mode DC power levels supplied at a particular voltage/current. Static power management systems condition the output voltage and current to levels that are appropriate for a particular circuit. When operated in a switched-mode, these power management systems are also used to cycle power within a given circuit at time periods that cause the circuit to “turn off” during time intervals when its functions are not absolutely needed by the larger system it serves. Power cycling is particularly important in mobile systems to extend battery life, and when refreshing and clocking data between random access memory and microprocessor systems, particularly in multi-core microprocessor architectures. The concepts presented herein are not limited to DC/DC power systems, and can be similarly applied to AC/DC inverter and AC/AC transformer circuitry with rudimentary understanding of those skilled in the art of power management.
Multi-processor core systems have particular relevance to the present invention. Localized high-speed computing systems co-locate microprocessor, memory, and micro-controller subsystem functions within a processing cell that is wired in parallel with other processor cells. Until recently, higher computing speeds are achieved by distributing instructions across all the cells to allow each cell to work simultaneously on an instruction packet. Fundamental limitations relating to the stability of the clock circuitry that times data transfers within and between each of the subsystems, and the speed and power levels at which external power management circuitry can supply power to the computing cell is now causing the microprocessor to be underutilized. These fundamental limitations now cause the microprocessor of a single cell to operate at 25%-30% of its utilization capacity. Utilization capacities are further reduced when microprocessors are arrayed in parallel. For instance, a 16 core microprocessor array will function slower than a 4 core microprocessor array. The under-utilization of localized microprocessor arrays has motivated the development of cloud computing architectures that distribute computational functions across a computer network, which open undesirable risks to data security in many computational applications. Therefore, it is desirable to provide switched-mode power levels at higher speeds, as well as stable clock circuitry to a single processor or a multi-core processor system.
Thermal management considerations are a principal impediment to achieving these objectives. Power management systems and processor cores generate heat that compromises performance when not adequately managed. The significant heat generated in power management circuitry having less than optimal efficiencies cause it to be physically isolated, typically on another board, from memory, microprocessor, controller circuitry, which generate large amounts of heat in their own right. The physical separation contributes to the less than optimal delivery of power at the speeds necessary to resolve these problems. Methods that produce higher efficiency power management modules which generate lower heat levels permit higher power levels to be supplied by placing the power management device in closer proximity to memory and microprocessor core circuitry. Co-location of high efficiency switched-mode power management devices with one or more processor cells also reduce overall system power losses through much shorter interconnect circuitry. Methods and apparatus that improve supplied power to a processor core are therefore desirable to the enhanced utilization of microprocessor arrays and the improved operational efficiency of high-speed computing systems.
Heat generated by the processor circuitry and any co-located power management device alters the timing of conventional clock circuitry. This causes a need for additional control circuitry to maintain stable clock functionality. Therefore, the development of clock circuitry that remains stable with varying temperature, and the introduction of additional means to reduce the power consumed by semiconductor die in electrical communication with co-located power management systems are also desirable.
1. Description Of The Prior Art
Hopper et al., U.S. Pat. No. 7,652,348 B1, “APPARATUS & METHOD FOR WAFER LEVEL FABRICATION OF HIGH VALUE INDUCTORS ON SEMICONDUCTOR IC's”, issued Jan. 1, 26, 2010, teach the assembly of inductor coils on semiconductor wafers containing active devices buried beneath the wafer surface using high permeability magnetic core material prepared from powder pastes.
Bose et al., U.S. Ser. No. 12/023,536, “METHOD AND SYSTEMS OF MULTI-CORE MICROPROCESSOR POWER MANAGEMENT AND CONTROL VIA PER-CHIPLET PROGRAMMABLE POWER MODES”, filed Jan. 31, 2008, published Aug. 6, 2009, as U.S. Pub. No. 2009/0199020 A1, instructs a system that manages power in a microprocessor core and an associated memory cache.
Ewing et al., U.S. Ser. No. 12/344,419, “POWER DISTRIBUTION, MANAGEMENT, AND MONITORING SYSTEMS AND METHODS”, filed Dec. 26, 2008, and published Sep. 17, 2009 as U.S. Pub. No. 2009/0234512 discloses the discrete assembly of a power management system that contains toroidal inductor coils.
Hughes et al., U.S. Ser. No. 12/356,624, “PROCESSOR POWER MANAGEMENT AND METHOD”, filed Jan. 21, 2009, and published Jul. 22, 2010 as U.S. Pub. No. 2010/0185820 A1, induces a sequence of sleep modes among multiple processors cores to optimize power utilization in under-utilized multi-core processor configurations (Hughes et al. '624).
Finkelstein et al., U.S. Ser. No. 12/263,421, “POWER MANAGEMENT FOR MULTIPLE PROCESSOR CORES”, filed Oct. 31, 2008, and published May 6, 2010, as U.S. Pub. No. 2010/0115304 A1, instructs techniques to manage power consumption locally in processor and the distribution of power among different power planes of a processor core based on energy-based considerations.
Yung-Hsiang, U.S. Ser. No. 11/713,889, “POWER MANAGEMENT IN COMPUTER OPERATING SYSTEMS”, filed Mar. 5, 2007, and published Oct. 18, 2007 as U.S. Pub. No. 2007/0245163 A1, instructs the use of selection policies to manage power distribution to components in a computer system.
Brittain et al., U.S. Ser. No. 11/463,743, “SYSTEMS AND METHODS FOR MEMORY POWER MANAGEMENT”, filed Aug. 10, 2006, and published Feb. 14, 2008 as 2008/0040563 A1, instructs systems for determining specific power consumption and usage levels in computer memory systems.
Borkar et al. U.S. Pat. No. 7,568,112, “POWER DELIVERY AND POWER MANAGEMENT OF MANY CORE PROCESSORS”, filed Sep. 9, 2005, uses multiple voltage regulators that may be integrated within the die or packaged with the die to manage power to a multi-microprocessor core system.
Ou, U.S. Ser. No. 10/236,700, “INDUCTOR FORMED ON A SILICON SUBSTRATE AND METHOD OF MANUFACTURING THE SAME”, filed Sep. 5, 2002 and published Jul. 3, 2003 as U.S. Pub. No. 2003/0122647 teaches the integration of inductor coils using methods that are compatible with CMOS semiconductor processes.
Evans et al., U.S. Pat. No. 5,543,773. “TRANSFORMERS AND COUPLED INDUCTORS WITH OPTIMUM INTERLEAVING”, issued Aug. 6, 1996, discloses the discrete assembly of toroidal inductor and transformer coils on a printed circuit board with optimal interleaving to minimize flux leakage and proximity losses as shown in FIG. 2.
2. Definition Of Terms
The term “active component” is herein understood to refer to its conventional definition as an element of an electrical circuit that that does require electrical power to operate and is capable of producing power gain.
The term “amorphous material” is herein understood to mean a material that does not comprise a periodic lattice of atomic elements, or lacks mid-range (over distances of 10's of nanometers) to long-range crystalline order (over distances of 100's of nanometers).
The terms “chemical complexity”, “compositional complexity”, “chemically complex”, or “compositionally complex” are herein understood to refer to a material, such as a metal or superalloy, compound semiconductor, or ceramic that consists of three (3) or more elements from the periodic table.
The term “chip carrier” is herein understood to refer to an interconnect structure built into a semiconductor substrate that contains wiring elements and active components that route electrical signals between one or more integrated circuits mounted on chip carrier's surface and a larger electrical system that they may be connected to.
The term “DDMOSFET” herein references its conventional meaning as a double-diffused dopant profile in conjunction with a field-effect transistor that uses a metal-oxide-semiconductor interface to modulate currents.
The terms “discrete assembly” or “discretely assembled” is herein understood to mean the serial construction of an embodiment through the assembly of a plurality of pre-fabricated components that individually comprise a discrete element of the final assembly.
The term “emf” is herein understood to mean its conventional definition as being an electromotive force.
The term “EMI” is herein understood to mean its conventional definition as electromagnetic interference.
The term “IGBT” herein references its conventional meaning as an insulated gate bipolar transistor.
The term “integrated circuit” is herein understood to mean a semiconductor chip into which a large, very large, or ultra-large number of transistor elements have been embedded.
The term “LCD” is herein understood to mean a method that uses liquid precursor solutions to fabricate materials of arbitrary compositional or chemical complexity as an amorphous laminate or free-standing body or as a crystalline laminate or free-standing body that has atomic-scale chemical uniformity and a microstructure that is controllable down to nanoscale dimensions.
The term “liquid precursor solution” is herein understood to mean a solution of hydrocarbon molecules that also contains soluble metalorganic compounds that may or may not be organic acid salts of the hydrocarbon molecules into which they are dissolved.
The term “microstructure” is herein understood to define the elemental composition and physical size of crystalline grains forming a material substance.
The term “MISFET” is herein understood to mean its conventional definition by referencing a metal-insulator-semiconductor field effect transistor.
The term “mismatched materials” is herein understood to define two materials that have dissimilar crystalline lattice structure, or lattice constants that differ by 5% or more, and/or thermal coefficients of expansion that differ by 10% or more.
The term “MOSFET” is herein understood to mean its conventional definition by referencing a metal-oxide-silicon field effect transistor.
The term “nanoscale” is herein understood to define physical dimensions measured in lengths ranging from 1 nanometer (nm) to 100's of nanometers (nm).
The term “passive component” is herein understood to refer to its conventional definition as an element of an electrical circuit that that does not require electrical power to operate and is not capable of producing power gain.
The term “power FET” is herein understood to refer to the generally accepted definition for a large signal vertically configured MOSFET and covers multi-channel (MUCHFET), V-groove MOSFET, truncated V-groove MOSFET, double-diffusion DMOSFET, modulation-doped transistors (MODFET), heterojunction transistors (HETFET), and insulated-gate bipolar transistors (IGBT).
The term “standard operating temperatures” is herein understood to mean the range of temperatures between −40° C. and +125° C.
The term “surface FET” is herein understood to understood by its conventional definition as a field effect transistor that uses electrodes applied to, and electronic dopant profiles patterned on the surface of and within a semiconductor layer to modulate current flows across the surface of the semiconductor layer.
The terms “tight tolerance” or “critical tolerance” are herein understood to mean a performance value, such as a capacitance, inductance, or resistance, that varies less than ±1% over standard operating temperatures.
In view of the above discussion, it would be beneficial to improve the operational efficiency of semiconductor die, including the utilization of processor cores, by shrinking their size, power consumption, using methods that enable reduced transistor counts, stable clock circuitry, and the delivery of higher power levels using high-frequency switched mode power. The present invention instructs the monolithic integration of low-loss high-power, high-speed switched-mode power management on a silicon carrier to improve the operational efficiency of semiconductor die, including processor cells, co-located on the silicon carrier.